ICS932S200 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
ICS932S200
Integrated Circuit Systems
'ICS932S200' PDF : 12 Pages View PDF
ICS932S200
PCI_STOP# Timing Diagram
PCI_STOP# is an input to the clock synthesizer and must be made synchronous to the clock driver PCICLK_F output.
It is used to turn off the PCI clocks for low power operation. PCI clocks are required to be stopped in a low state and
started such that a full high pulse width is guaranteed. ONLY one rising edge of PCICLK_F is allowed after the clock
control logic switched for the PCI outputs to become enabled/disabled.
CPUCLK
(internal)
PCICLK
(internal)
CPU_STOP#
PCI_STOP#
PD#
PCICLK
(externall)
Notes:
1. All timing is referenced to CPUCLK.
2. Internal means inside the chip.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high state.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
0427C—07/03/02
5
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