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Part Name
Description
ICS93776YFLF-T View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
ICS93776YFLF-T
Low Cost DDR Phase Lock Loop Zero Delay Buffer
Integrated Circuit Systems
'ICS93776YFLF-T' PDF : 8 Pages
View PDF
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ICS9377 6
Bytes 2 to 6 are reseved power up default = 1. This allows operation with main clock.
BYTE
Affected Pin
0
Pin #
Name
Bit 7
2, 1
DDR0(T&C)
Bit 6
4, 5
DDR1(T&C)
Bit 5
-
-
Bit 4
-
-
Bit 3 13, 14
DDR2(T&C)
Bit 2 26, 27
DDR5(T&C)
Bit 1
-
-
Bit 0 24, 25
DDR4(T&C)
Note: PWD = Power Up Default
BYTE
Affected Pin
1
Pin #
Name
Bit 7
-
-
Bit 6 16,17
DDR3(T&C)
Bit 5
-
-
Bit 4
-
-
Bit 3
-
-
Bit 2
-
-
Bit 1
-
-
Bit 0
-
-
Note: PWD = Power Up Default
Control Function
Output Control
Output Control
Reserved
Reserved
Output Control
Output Control
Reserved
Output Control
Control Function
Reserved
Output Control
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
X
X
RW
RW
X
RW
Bit Control
0
1
DISABLE ENABLE
DISABLE ENABLE
-
-
-
-
DISABLE ENABLE
DISABLE ENABLE
-
-
DISABLE ENABLE
PWD
1
1
1
1
1
1
1
1
Type
X
RW
X
X
RW
X
RW
X
Bit Control
0
1
-
-
DISABLE ENABLE
-
-
-
-
-
-
-
-
-
-
-
-
PWD
1
1
0
0
0
0
0
0
0793A—03/08/05
6
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