ICS94225 View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS94225' PDF : 18 Pages View PDF
ICS94225
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94225. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS94225 internally. PCICLK clocks are stopped in a low state and started with
a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-runningl)
CPU_STOP#
PCI_STOP#
PWR_DWN#
PCICLK
(External)
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94225 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS94225.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
0445B—08/01/03
16
Share Link: 
