IDTCV115C View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
MFG CO.
'IDTCV115C' PDF : 19 Pages View PDF
IDTCV115C
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PLL FREQUENCY PROGRAMMING PROCEDURES
The user changes PLL frequency through Soft Alarm or Hard Alarm. The Watch Dog circuit has to be enabled. Based on their application, the user may
enable either one or both of the alarms.
User presets the CPU PLL Mode and N, and SRC PLL N value:
1. Set CPU PLL Mode, CB1 and CB2, byte 17
2. Set CPU PLL N, CN1 and CN2, byte 18 and byte 19
3. Set SRC(PCI Express) PLL N, PN1 and PN2, byte 21, 22
User selects the frequency for Soft Alarm and Hard Alarm, if enabled respectively:
4. Select Soft Alarm frequency, byte 23
5. Select Hard Alarm frequency, byte 24
User sets the Timer and enables the WD circuit for frequency switch:
6. Set Hard Alarm Timer, byte 25
7. Set Soft Alarm Timer, byte 26
8. Enable Soft and Hard Alarm, byte 27
9. Enable Watch Dog (WDE), byte 27
• WDE Disable resets WDSRB and WDHRB.
• PCI CLK is selectable from SRC PLL or SATA PLL, byte 5 bit 6. If from SRC PLL, PCI frequency = 1/3 of SRC frequency. If from SATA, PCI
is fixed to 3 selections, 33MHz, 36MHz and 40MHz, byte 5 bit[5:4].
WD SOFT AND HARD ALARM/TIME OUT OPERATION
WD HARD ALARM TIMER [7:0]
WD SOFT ALARM TIMER [3:0]
WDE
Trigger Watch Dog Circuit
If Soft Alarm Enabled (byte 27):
Set WDSRB (byte 6)
Load CPU N and Mode
selections into PCU PLL
Load SRC N selection
into SRC PLL
If Hard Alarm Enabled (byte 27):
Set WDHRB (byte 6)
Load CPU N and Band selections into PCU PLL
Load SRC N selections into SRC PLL
If Hard Alarm Relatch Enabled:
Latch FSC, B, A
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