INT100 View Datasheet(PDF) - Power Integrations, Inc
Part Name
Description
MFG CO.
'INT100' PDF : 12 Pages View PDF
General Circuit Operation
One phase of a three-phase motor drive
circuit is shown in Figure 4 to illustrate
an application of the INT100. The LS
IN signal directly controls MOSFET
Q1. The HS IN signal controls MOSFET
Q2 via the high voltage level shift
transistors communicating with the high-
side driver. The INT100 will ignore
input signals that would command both
Q1 and Q2 to conduct simultaneously,
protecting against shorting the HV+ bus
to HV-.
Local bypassing for the low-side driver
is provided by C1. Bootstrap bias for the
high-side driver is provided by D1 and
C2. Slew rate and effects of parasitic
oscillations in the load waveforms are
controlled by resistors R1 and R2.
The inputs are designed to be compatible
with 5 V CMOS logic levels and should
not be connected to VDD. Normal CMOS
power supply sequencing should be
observed. The order of signal application
should be VDD, logic signals, and then
HV+. VDD should be supplied from a
low impedance voltage source.
The output returns (HS RTN and LS
RTN) are isolated from one another by
the internal high-voltage MOSFET level
shifters. The level shift circuitry is
designed to operate properly even when
the HS RTN swings as much as 5 V
below the LS RTN pin with VDDH biased
at 15 V. The INT100 will also safely
tolerate more negative voltages (as low
as -VDDH below LS RTN).
Maximum frequency of operation is
limited by power dissipation due to high-
voltage switching, gate charge, and bias
power. Figure 5 indicates the maximum
switching frequency as a function of
input voltage and gate charge. For higher
ambient temperatures, the switching
frequency should be derated linearly.
INT100
The bootstrap capacitor must be large
enough to provide bias current over the
entire on-time of the high-side driver
without significant voltage sag or decay.
The high-side MOSFET gate charge
must also be supplied at the desired
switching frequency. Figure 6 shows
the maximum high-side on-time versus
gate charge of the external MOSFET.
Applications with extremely long high-
side on times require special techniques
discussed in AN-10.
The high-side driver is latched on and
off by the edges of the appropriate low-
side logic signal. The high-side driver
will latch off and stay off if the bootstrap
capacitor discharges below the
undervoltage lockout threshold.
Undervoltage lockout-induced turn off
can occur during conditions such as
power ramp up, motor start, or low speed
operation.
CBOOTSTRAP vs. ON TIME
1000
100
10
QG = 100 nC
1
QG = 20 nC
0.1
0.01
0.01
0.1
1
10
100
High Side On Time (ms)
Figure 6. High-side On Time versus Bootstrap Capacitor.
5 C
6/96
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