INTEL82801E View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'INTEL82801E' PDF : 84 Pages View PDF
Intel® 82801E C-ICH
Table 6. 82801E C-ICH Signal Description (Sheet 3 of 11)
Signal
FERR#
FRAME#
FWH[3:0]
/LAD[3:0]
FWH[4]
/LFRAME#
GNT[3:0]#
GNT[5]#
/GNT[B]#
/GPIO[17]#
GNT[A]#
/GPIO[16]
/GNT[B]#
/GNT[5]#
/GPIO[17]
GPIO[1:0]
GPIO[3:2]
GPIO[5:4]
GPIO[6]
GPIO[7]
GPIO[8]
GPIO[10:9]
GPIO[11]
GPIO[13:12]
GPIO[15:14]
GPIO[17:16]
GPIO[20:18]
GPIO[21]
GPIO[22]
GPIO[23]
Type
I
I/O
Description
Numeric Coprocessor Error: This signal is tied to the coprocessor error
signal on the processor. FERR# is only used if the 82801E C-ICH
coprocessor error reporting function is enabled in the General Control
Register (Device 31:Function 0, Offset D0, bit 13). If FERR# is asserted, the
82801E C-ICH generates an internal IRQ13 to its interrupt controller unit. It is
also used to gate the IGNNE# signal to ensure that IGNNE# is not asserted to
the processor unless FERR# is active. FERR# requires an external weak
pull-up to ensure a high level when the coprocessor error function is disabled.
Cycle Frame: The current Initiator asserts FRAME# to indicate the beginning
and duration of a PCI transaction. While the initiator asserts FRAME#, data
transfers continue. When the initiator deasserts FRAME#, the transaction is in
the final data phase. FRAME# is an input to the 82801E C-ICH when the
82801E C-ICH is the target, and FRAME# is an output from the 82801E
C-ICH when the 82801E C-ICH is the Initiator. FRAME# remains tri-stated by
the 82801E C-ICH until driven by an Initiator.
I/O Firmware Hub Signals: These signals are muxed with LPC address signals.
I/O Firmware Hub Signals: This signal is muxed with the LPC LFRAME# signal.
PCI Grants: The 82801E C-ICH supports up to four masters on the PCI bus.
GNT[5]# is muxed with PC/PCI GNT[B]# (must choose one or the other, but
not both). If not needed for PCI or PC/PCI, GNT[5]# can instead be used as a
O GPIO.
Pull-up resistors are not required on these signals. If pullups are used, they
should be tied to the Vcc3_3 power rail. GNT[B]#/GNT[5]#/GPIO[17] has an
internal pull-up.
PC/PCI DMA Acknowledges [A:B]: This grant serializes an ISA-like DACK#
for the purpose of running DMA/ISA master cycles over the PCI bus. This is
used by devices such as PCI-based Super I/O or audio codecs which need to
O perform legacy 8237 DMA but have no ISA bus.
When not used for PC/PCI, these signals can be used as General Purpose
Outputs. GNTB# can also be used as the fourth PCI bus master grant output.
These signal have internal pull-up resistors.
I
Fixed as Input only. Main Power Well. Can instead be used for PC/PCI
REQ[A:B]#. GPIO[1] can also alternatively be used for PCI REQ[5]#.
Not implemented.
I
Fixed as Input only. Main power well. Can be used instead as PIRQ[G:H]#.
I
Fixed as Input only. Main power well.
I
Fixed as Input only. Main power well. Not muxed.
I
Fixed as Input only. Main power well. Not muxed.
I
Not implemented.
I
Fixed as Input only. Main power well. Can instead be used for SMBALERT#.
I
Fixed as Input only. Main power well. Not muxed.
I
Not implemented.
Fixed as Output only. Main Power Well. Can instead be used for PC/PCI
O GNT[A:B]#. GPIO[17] can also alternatively be used for PCI GNT[5]#.
Integrated pull-up resistor.
O Fixed as Output only. Main power well.
O Fixed as Output only. Main power well.
OD Fixed as Output only. Main power well. Open-drain output.
O Fixed as Output only. Main power well.
Advance Information Datasheet
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