IR3Y48A1 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'IR3Y48A1' PDF : 34 Pages View PDF
Clock Timing Variations by Register
Setting
The variations of clock timings when it is inverted
by register settings.
1. No inversion
(Mode (1) Register D6 = 0, Mode (2) Register
D2 = 0; Default) (Upper figure)
IR3Y48A1
2. ADCK inversion
(Mode (1) Register D6 = 1, Mode (2) Register
D2 = 0) (Lower figure)
CCD
SHR
SHD
ADCK
OUTCK
DO0-DO9
Pulse Control (Default : No Inversion)
CCD
SHR
SHD
ADCK
OUTCK
DO0-DO9
Pulse Control (ADCK Inversion)
32
Share Link: 
