IR3Y48A1 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'IR3Y48A1' PDF : 34 Pages View PDF
CDS (Correlated Double Sampling) Circuit
Connect the signal from a CCD sensor to the
CCDIN pin via a capacitor and connect the REFIN
pin to AVSS via a capacitor.
The CDS circuit holds the CCD precharge
(reference) level at SHR pulse, then it samples the
CCD pixel data at SHD pulse. Correlated
(common) noise is removed by the subtracting
IR3Y48A1
precharge level from the pixel data level.
CDS can choose a gain setting from 0, 6.02, 12 or
–1.94 dB (Mode (3) Register D4 & D5 bits). A CDS
gain is controlled separately from a PGA gain. To
reduce noise as much as possible, it is
recommended to increase the CDS gain first before
increasing the PGA gain.
CDS Circuit
Reference Clock (SHR)
Data Clock (SHD)
REFIN
CCD
CCDIN
CDS
CDS Output
= V (CDS)
= V (Data) – V (Precharge)
CDS Operation
Reset
Pulse
Reset
Pulse
V (Precharge)
V (CDS) V (Data)
SHR
SHD
SHR
SHD
SIG
SIG
fSMAX = 18 MHz/tSMIN = 55 ns
MAX. Level
7
Share Link: 
