ISPGDX2 View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
MFG CO.
'ISPGDX2' PDF : 72 Pages View PDF
Lattice Semiconductor
ispGDX2 Family Data Sheet
ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters1 (Continued)
Over Recommended Operating Conditions
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-5
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
tOELSi
tOELSi_PT
tOESi
tOESi_PT
tOESRPWi
Latch Setup Time (Global Gate)
1.40 — 1.40 — 1.40 — 2.33 — ns
Latch Setup Time (Product Term Gate)
1.00 — 1.00 — 1.00 — 1.67 — ns
Register Setup Time (Global Clock)
1.00 — 1.00 — 1.40 — 2.33 — ns
Register Setup Time (Product Term Clock) 1.00 — 1.00 — 1.00 — 1.67 — ns
Asynchronous Set/Reset Pulse Width
— 2.50 — 2.50 — 2.50 — 4.17 ns
Timing v.2.2
1. Internal parameters are not tested and are for reference only. Refer to the timing model in this data sheet for details.
2. tPLL_DELAY is the unit of increment by which the clock signal can be incremented. The PLL can adjust the clock signal by up to tRANGE (as
given in the sysCLOCK PLL Timing section) in either direction in steps of size tPLL_DELAY.
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