ISPGDX2 View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

MFG CO.

ISPGDX2

High Performance Interfacing and Switching

Lattice Semiconductor 

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Lattice Semiconductor

ispGDX2 Family Data Sheet

ispGDX2V/B/C, ispGDX2EV/EB/EC Timing Adjusters

Parameter

Optional Adders

tINDIO

tPLL_SEC_DELAY

tIOO Output Adjusters

Slow Slew

LVTTL_out

LVCMOS_18_4mA_out

LVCMOS_18_5.33mA_out

LVCMOS_18_8mA_out

LVCMOS_18_12mA_out

LVCMOS_25_4mA_out

LVCMOS_25_5.33mA_out

LVCMOS_25_8mA_out

LVCMOS_25_12mA_out

LVCMOS_25_16mA_out

LVCMOS_33_4mA_out

LVCMOS_33_5.33mA_out

LVCMOS_33_8mA_out

LVCMOS_33_12mA_out

LVCMOS_33_16mA_out

LVCMOS_33_20mA_out

AGP_1X_out

BLVDS_out

CTT25_out

CTT33_out

GTL+_out

HSTL_I_out

HSTL_III_out

HSTL_IV_out

Description

-3

-32

-35

-5

Min. Max. Min. Max. Min. Max. Min. Max. Units

Input Delay

Secondary PLL Output

Delay

— 1.50 — 1.50 — 1.50 — 2.50 ns

— 1.30 — 1.30 — 1.30 — 1.30 ns

Using Slow Slew (LVTTL and

LVCMOS Outputs Only)

—

0.90

—

0.90

—

0.90

—

0.90

ns

Using 3.3V TTL Drive

— 1.20 — 1.20 — 1.20 — 1.20 ns

Using 1.8V CMOS Standard,

4mA Drive

—

0.30

—

0.30

—

0.30

—

0.30

ns

Using 1.8V CMOS Standard,

5.33mA Drive

—

0.30

—

0.30

—

0.30

—

0.30

ns

Using 1.8V CMOS Standard,

8mA Drive

—

0.00

—

0.00

—

0.00

—

0.00

ns

Using 1.8V CMOS Standard,

12mA Drive

—

0.00

—

0.00

—

0.00

—

0.00

ns

Using 2.5V CMOS Standard,

4mA Drive

—

1.20

—

1.20

—

1.20

—

1.20

ns

Using 2.5V CMOS Standard,

5.33mA Drive

—

1.00

—

1.00

—

1.00

—

1.00

ns

Using 2.5V CMOS Standard,

8mA Drive

—

0.40

—

0.40

—

0.40

—

0.40

ns

Using 2.5V CMOS Standard,

12mA Drive

—

0.40

—

0.40

—

0.40

—

0.40

ns

Using 2.5V CMOS Standard,

16mA Drive

—

0.40

—

0.40

—

0.40

—

0.40

ns

Using 3.3V CMOS Standard,

4mA Drive

—

1.20

—

1.20

—

1.20

—

1.20

ns

Using 3.3V CMOS Standard,

5.33mA Drive

—

1.20

—

1.20

—

1.20

—

1.20

ns

Using 3.3V CMOS Standard,

8mA Drive

—

0.80

—

0.80

—

0.80

—

0.80

ns

Using 3.3V CMOS Standard,

12mA Drive

—

0.60

—

0.60

—

0.60

—

0.60

ns

Using 3.3V CMOS Standard,

16mA Drive

—

0.60

—

0.60

—

0.60

—

0.60

ns

Using 3.3V CMOS Standard,

20mA Drive

—

0.30

—

0.30

—

0.30

—

0.30

ns

Using AGP 1x Standard

— 0.60 — 0.60 — 0.60 — 0.60 ns

Using Bus Low Voltage Dif-

ferential Signaling (BLVDS)

— 1.00 — 1.00 — 1.00 — 1.00

ns

Using CTT 2.5v

— 0.30 — 0.30 — 0.30 — 0.30 ns

Using CTT 3.3v

— 0.20 — 0.20 — 0.20 — 0.20 ns

Using GTL+

— 0.50 — 0.50 — 0.50 — 0.50 ns

Using HSTL 2.5V, Class I

— 0.50 — 0.50 — 0.50 — 0.50 ns

Using HSTL 2.5V, Class III — 0.60 — 0.60 — 0.60 — 0.60 ns

Using HSTL 2.5V, Class IV — 0.60 — 0.60 — 0.60 — 0.60 ns

36

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