IT8502F View Datasheet(PDF) - ITE Tech. INC.

Part Name

Description

MFG CO.

IT8502F

Embedded Controller

ITE Tech. INC. 

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IT8502E/F/G

Table 6-14. Host View Register Map via Index-Data I/O, PMC2 Logical Device............................................ 63

Table 6-15. Host View Register Map via Index-Data I/O, PMC3 Logical Device............................................ 64

Table 6-16. Host View Register Map via Index-Data I/O Pair, SSPI Logical Device ...................................... 67

Table 6-17. Mapped Host Memory Address ................................................................................................. 71

Table 6-18. Corresponding Table of SPI Flash Power-on Detection ............................................................. 78

Table 6-19. EC View Register Map, SMFI .................................................................................................... 79

Table 6-20. Host View Register Map, SMFI.................................................................................................. 93

Table 6-21. Host View Register Map, SWUC ............................................................................................... 98

Table 6-22. EC View Register Map, SWUC................................................................................................ 101

Table 6-23. Host View Register Map, KBC................................................................................................. 108

Table 6-24. EC View Register Map, KBC ................................................................................................... 109

Table 6-25. Host View Register Map, PMC ................................................................................................ 117

Table 6-26. EC View Register Map, PMC .................................................................................................. 120

Table 7-1. 8032 Port Usage ...................................................................................................................... 131

Table 7-2. System Interrupt Table .............................................................................................................. 133

Table 7-3. Timer 2 Modes of Operation...................................................................................................... 139

Table 7-4. Serial Port Signals .................................................................................................................... 141

Table 7-5. Selecting the Baud Rate Generator(s) ....................................................................................... 143

Table 7-6. Internal RAM Map ..................................................................................................................... 145

Table 7-7. EC View Register Map, INTC .................................................................................................... 162

Table 7-8. INTC Interrupt Assignments ...................................................................................................... 172

Table 7-9. EC View Register Map, WUC.................................................................................................... 176

Table 7-10. WUC Input Assignments ......................................................................................................... 182

Table 7-11. KSI/KSO as GPIO List............................................................................................................. 185

Table 7-12. EC View Register Map, KB Scan............................................................................................. 186

Table 7-13. EC View Register Map, GPIO.................................................................................................. 192

Table 7-14. GPIO Alternate Function ......................................................................................................... 198

Table 7-15. EC View Register Map, ECPM ................................................................................................ 203

Table 7-16. EC View Register Map, SMBus ............................................................................................... 231

Table 7-17. EC View Register Map, PS/2................................................................................................... 241

Table 7-18. EC View Register Map, DAC ................................................................................................... 244

Table 7-19. ADC Configuration .................................................................................................................. 247

Table 7-20. EC View Register Map, ADC ................................................................................................... 249

Table 7-21. Detail Step of ADC Channel Conversion ................................................................................. 258

Table 7-22. EC View Register Map, PWM.................................................................................................. 264

Table 7-23. EC View Register Map, TMR................................................................................................... 279

Table 7-24. EC View Register Map, EC2I .................................................................................................. 287

Table 7-25. EC View Register Map, ETWD ................................................................................................ 293

Table 7-26. EC View Register Map, GCTRL .............................................................................................. 298

Table 7-27. Host View Register Map, BRAM.............................................................................................. 309

Table 7-28. Host View Register Map via Index-Data I/O Pair, BRAM Bank 0 .............................................. 309

Table 7-29. Host View Register Map via Index-Data I/O Pair, BRAM Bank 1 .............................................. 309

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IT8502E/F/G V0.7.7

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