K60P100M100SF2RM View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

MFG CO.

K60P100M100SF2RM

K60 Sub-Family Reference Manual

Freescale Semiconductor 

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Section Number

Title

Page

37.2 Memory Map and Register Definition..........................................................................................................................899

37.2.1 VREF Trim Register (VREF_TRM)............................................................................................................900

37.2.2 VREF Status and Control Register (VREF_SC)..........................................................................................901

37.3 Functional Description..................................................................................................................................................902

37.3.1 Voltage Reference Disabled, SC[VREFEN] = 0.........................................................................................902

37.3.2 Voltage Reference Enabled, SC[VREFEN] = 1..........................................................................................902

37.4 Initialization/Application Information..........................................................................................................................903

Chapter 38

Programmable Delay Block (PDB)

38.1 Introduction...................................................................................................................................................................905

38.1.1 Features........................................................................................................................................................905

38.1.2 Implementation............................................................................................................................................906

38.1.3 Back-to-back Acknowledgement Connections............................................................................................907

38.1.4 DAC External Trigger Input Connections...................................................................................................907

38.1.5 Block Diagram.............................................................................................................................................907

38.1.6 Modes of Operation.....................................................................................................................................909

38.2 PDB Signal Descriptions..............................................................................................................................................909

38.3 Memory Map and Register Definition..........................................................................................................................909

38.3.1 Status and Control Register (PDBx_SC).....................................................................................................911

38.3.2 Modulus Register (PDBx_MOD).................................................................................................................913

38.3.3 Counter Register (PDBx_CNT)...................................................................................................................914

38.3.4 Interrupt Delay Register (PDBx_IDLY)......................................................................................................914

38.3.5 Channel n Control Register 1 (PDBx_CHnC1)...........................................................................................915

38.3.6 Channel n Status Register (PDBx_CHnS)...................................................................................................916

38.3.7 Channel n Delay 0 Register (PDBx_CHnDLY0)........................................................................................917

38.3.8 Channel n Delay 1 Register (PDBx_CHnDLY1)........................................................................................917

38.3.9 DAC Interval Trigger n Control Register (PDBx_DACINTCn).................................................................918

38.3.10 DAC Interval n Register (PDBx_DACINTn)..............................................................................................918

38.3.11 Pulse-Out n Enable Register (PDBx_POnEN).............................................................................................919

K60 Sub-Family Reference Manual, Rev. 6, Nov 2011

32

Freescale Semiconductor, Inc.

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