KB2512 View Datasheet(PDF) - Samsung
Part Name
Description
MFG CO.
'KB2512' PDF : 36 Pages View PDF
KB2512
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
The KB2512 also includes a lock/unlock identification block which senses in real time whether PLL1 is locked or
not on the incoming horizontal sync signal. The resulting information is available on Hlockout (see sync processor).
The block function is described in figure 5.
When PLL1 is unlocked, It forces Hlockout to leave high.
The lock/unlock information is also available throw I2C read.
PLL2
The PLL2 ensures a constant position of the shaped Flyback signal in comparison with the sawtooth of the VCO
(Figure 8). The phase comparator of PLL2 (phase type comparator) is followed by a charge pump (typical output
current:0.5mA). The Flyback input is composed of an NPN transistor. This input must be current driven. The
maximum recommended input current is 5mA (see Figure 9).
The duty cycle is adjustable through I2C from 30% to 60%. For start up safe operation, initial duty cycle (after
power on reset) is 60% in order to avoid having a too long conduction period of the horizontal scanning transistor.
The maximum storage time (Ts max.) is (0.44TH-TFLY/2). Typically, TFLY/TH is around 20% which means that Ts
max is around 34% of TH.
H osc
Sawtooth
7/8TH
1/8TH
6.4V
3.7V
Flyback
Internally
Shaped Flyback
H drive
Ts
Duty Cycle
1.6V
Figure 8. PLL2 Timing Diagram
HFLY 12
20KΩ
400Ω
Q1
GND 0V
Figure 9. Flyback Input Electrical Diagram
27
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