KE5BLME064 View Datasheet(PDF) - KAWASAKI MICROELECTRONICS
Part Name
Description
MFG CO.
'KE5BLME064' PDF : 53 Pages View PDF
Kawasaki LSI
64K Longest Match Search Engine (KE5BLME064)
the large one.
PRELIMINARY
Contrary, the minimum Insertion rate is about 1.4k entries per second after the Initialize
command, this is on the condition that each new IP address data is inserted one by one
in large the order.
When both of data A and data B have the same IP data, it is preferable to insert the
data with the small value of PL (prefix length –1) previously . However, this is not to
required.
The typical Insertion/Deletion rate during search operations is about 500 entries per
second and worst Insertion/Deletion rate is about 250 entries per second. The
maximum waiting time between Insertion/Deletion commands is about 30msec (at
66Mhz system clock operation).
4.8. Search via CPU Port
A search can be performed with the CPU port commands, independently of the Input
port operation. Apply a search key data to WR0-2 to execute the Search command.
Upon completion of a table lookup, associated data will be written to RR0-1; and both
ML (prefix-length minus one) and hit-or-miss-hit information will be written to RR2.
The command execution can be confirmed by monitoring the CCMPN pin status;
before proceeding with subsequent commands, ensure that the CCMPN pin is
changed to Low.
4.9. Interruption
Some statues of interrupt are defined in this device, that can be heard of by reading
the STAT1 register. Also the generation of interrupt can be known according to the
signal of IRQN pin when the interrupt with IRQN pin is defined in CNTL register.
When the STAT1 register is red, the value of STAT1 register should revert each bit to
“0” and Interrupt with IRQN pin should be cleared.
Refer to “6.2. Register Description” for the interrupt event with IRQN pin which can
concretely be defined. Interruption is not accomplished unless one of the conditions is
met, as described in “6.2. Register Description.” For instance, setting both bit 2 and bit
0 of the CNTL register to “1” activates the Interrupt operation upon completion of either
the Initialize command or the table fulfillment process.
Version 2.5.4
Proprietary and Confidential
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