Micrel
Timing Diagrams
10BaseT M II Transmit Timing
TXC
tHD2
TXEN
tSU2
tHD1
T X D [3:0]
CRS
tSU1
tCRS1
T X P /T X M
tLAT
V a lid
D a ta
SQE Timing
TXC
TXEN
COL
tSQE
tSQEP
tSU1
tSU2
tHD1
tHD2
tCRS1
tCRS2
tLAT
tSQE
tSQEP
TXD[3:0] Setup to TXC High
TXEN Setup to TXC High
TXD[3:0] Hold after TXC High
TXEN Hold after TXC High
TXEN High to CRS asserted latency
TXEN Low to CRS de-asserted latency
TXEN High to TXP/TXM output (TX latency)
COL (SQE) Delay after TXEN de-asserted
COL (SQE) Pulse Duration
KSZ8001
tCRS2
m in.
10ns
10ns
0ns
0ns
typ. max.
4BT
8BT
4BT
2.5us
1.0us
June 2009
Revision 1.04
36