L3000S View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

L3000S

SUBSCRIBER LINE INTERFACE KIT

STMicroelectronics 

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L3000S - L3030

ELECTRICAL CHARACTERISTICS (refer to the test circuits of the Figure 12, VDD = + 5V, VSS = -

5V, VB+ = + 72V, VB– = – 48V, Tamb = + 25oC, TTX FILT = 1kΩ)

Symbol

Parameter

Test Conditions

Min. Typ. Max. Unit

STAND-BY

Vls

Output Voltage at L3000S

Terminals

Iline = 0mA

Iline = 5mA

30.0

40.0

V

28.2

38.5

V

Ilcc

Short Circuit Current

DATA IN (note 1) 000X00X1

5

Iot

On/off-hook Detection Threshold

5

Vls

Symmetry to Ground

Iline = 0mA

8.5

mA

8.5

mA

.75

V

STAND BY DENIAL

Ilcc

Short Circuit Current

DATA IN 000X00X0

2

mA

DC OPERATION - NORMAL BATTERY (VTTX = 2VRMS, low level)

Vlo

Output Voltage at L3000S

Iline = 0mA

Terminals Ilim = 70mA Data in Iline = 20mA

1000X010

Iline = 50mA

Ilim

Current Programmed Through

the Digital Inter.

Io

On-hook Detection Threshold

If

Off-hook Detection Threshold

Ilgk

Longitudinal Line Current with

GK Detect

31.0

35.0

V

24.0

28.8

V

2.5

17.5

V

– 10% Ilim + 15% mA

8

mA

12

mA

10

17

26

mA

DC OPERATION - BOOST BATTERY

Vlo

Output Voltage at L3000S

Terminals

Iline = 0mA

Iline = 20mA

86

95.6

V

68.6

81

V

AC OPERATION

Ztx

Zrx

THD

Sending Output Impedance

4 Wire Side

Receiving Input Impedance

4 Wire Side

Signal Distorsion at 2W and 4W

Terminals

10

Ω

100

kΩ

0.5

%

R1

2W Return Loss

f = 300 to 3400Hz

22

dB

Thl

Trans Hybrid Loss

f = 300 to 3400Hz

24

dB

Gs

Sending Gain

Vso = 0dBm f = 1020Hz

Norm. Polarity

– 0.25

Gsf

Sending Gain Flatness versus f = 300 to 3400Hz Respect

– 0.1

Frequency

to 1020Hz

Gsl

Sending Gain Linearity

fr = 1020Hz,

Vsoref = –10dBm

Vso = + 4 /– 40dBm

– 0.1

dB

+ 0.25

+ 0.1 dB

+ 0.1 dB

Gr

Receiving Gain

Grf

Receiving Gain Flatness

Vri = 0dBm f = 1020Hz

Norm. Polarity

dB

– 0.25 0 + 0.25

f = 300 to 3400Hz Respect

to 1020

– 0.1

+ 0.1 dB

No tes : 1. The data into t he digital interface of L3030 are send i n serial mode. T he f ormat of dat a is the foll ow ing :

a) DAT A IN : the bit at left side is BIT 0 of the wri ting w ord, whil e the bit at the ri ght si de i s B IT 7.

b) DAT A OUT : the bit at the left side is BI T0 of the reading wor d, whil e the bit at the ri ght i s BI T4.

When appear a symbol X, the val ue of the bit don’ t care.

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