Application information
Figure 4. Reset timing diagram
Wi
Vo < trr
trr
Vcr
Res
Tosc
trd = 512 Tosc
L4989
Vout_th
Vrhth
Vrlth
3.3
Watchdog
t(s) A connected microcontroller is monitored by the watchdog input Wi. If pulses are missing,
c the Reset output pin is set to low. The pulse sequence time can be set within a wide range
u with the external capacitor, Ctw. The watchdog circuit discharges the capacitor Ctw, with the
d constant current Icwd. If the lower threshold Vwlth is reached, a watchdog reset is
ro generated. To prevent this the microcontroller must generate a positive edge during the
P discharge of the capacitor before the voltage has reached the threshold Vwlth. In order to
te calculate the minimum time t, during which the micro-controller must output the positive
edge, the following equation can be used:
sole (Vwhth-Vwlth) x Ctw = Icwd x t
Ob Every Wi positive edge switches the current source from discharging to charging. The same
- happens when the lower threshold is reached. When the voltage reaches the upper
t(s) threshold, Vwhth, the current switches from charging to discharging. The result is a
saw-tooth voltage at the watchdog timer capacitor Ctw.
uc Figure 5. Watchdog timing diagram
Prod Wi
te twop
le Vwhth
Vcw
o Vwlth
s Vwlth
Ob twol
Res
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