L4C381JC15 View Datasheet(PDF) - LOGIC Devices
Part Name
Description
MFG CO.
'L4C381JC15' PDF : 12 Pages View PDF
DEVICES INCORPORATED
L4C381
16-bit Cascadable ALU
SWITCHING CHARACTERISTICS — COMMERCIAL OPERATING RANGE (0°C to +70°C)
GUARANTEED MAXIMUM COMBINATIONAL DELAYS Notes 9, 10 (ns)
To Output
L4C381-20
L4C381-15
From Input
FTAB = 0, FTF = 0
Clock
C0
S2-S0, OSA, OSB
F15-F0 P, G OVF, Z C16 F15-F0 P, G OVF, Z C16
11 20 20 20 11 15 15 15
— — 14 14 — — 13 13
— 18 20 18 — 14 15 14
FTAB = 0, FTF = 1
Clock
C0
S2-S0, OSA, OSB
20 20 20 20 15 15 15 15
18 — 14 14 14 — 13 13
20 18 20 18 15 14 15 14
FTAB = 1, FTF = 0
A15-A0, B15-B0
Clock
C0
S2-S0, OSA, OSB
— 16 20 17 — 14 15 14
11 — — — 11 — — —
— — 14 14 — — 13 13
— 18 20 18 — 14 15 14
FTAB = 1, FTF = 1
A15-A0, B15-B0
20 16 20 17 15 14 15 14
Clock (OSA, OSB = 0) 20 20 20 20 15 15 15 15
C0
18 — 14 14 14 — 13 13
S2-S0, OSA, OSB
20 18 20 18 15 14 15 14
GUARANTEED MINIMUM SETUP AND HOLD TIMES WITH RESPECT TO CLOCK RISING EDGE Notes 9, 10 (ns)
L4C381-20
L4C381-15
FTAB = 0 FTAB = 1 FTAB = 0 FTAB = 1
Input
Setup Hold Setup Hold Setup Hold Setup Hold
A15-A0, B15-B0
5
0
14 0
5
0
12 0
C0
12 0
12 0
10 0
10 0
S2-S0, OSA, OSB
15 0
15 0
12 0
12 0
ENA, ENB, ENF
5
0
5
0
5
0
5
0
TRI-STATE ENABLE/DISABLE TIMES Notes 9, 10, 11 (ns)
L4C381-20 L4C381-15
tENA
8
6
tDIS
8
6
CLOCK CYCLE TIME AND PULSE WIDTH Notes 9, 10 (ns)
L4C381-20 L4C381-15
Minimum Cycle Time
18
14
Highgoing Pulse
5
4
Lowgoing Pulse
5
4
Arithmetic Logic Units
5
08/16/2000–LDS.381-P
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