L5985 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L5985' PDF : 36 Pages View PDF
L5985
5.4.1
Application informations
Type III compensation network
The methodology to stabilize the loop consists of placing two zeros to compensate the effect
of the LC double pole, so increasing phase margin; then to place one pole in the origin to
minimize the dc error on regulated output voltage; finally to place other poles far away the
zero dB frequency.
In Figure 10 the type III compensation network is shown. This network introduces two zeros
(fZ1, fZ2) and three poles (fP0, fP1, fP2). They expression are:
Equation 16
fZ1 = 2----π-----⋅---C-----3----⋅--1-(--R-----1----+-----R----3----),
fZ2 = 2----π-----⋅---R--1---4----⋅---C----4-
Equation 17
fP0 = 0,
fP1
=
--------------1--------------- ,
2π ⋅ R3 ⋅ C3
fP2
=
---------------------1----------------------
2π
⋅
R4
⋅
-C-----4----⋅---C-----5--
C4 + C5
Figure 10. Type III compensation network
In Figure 11 the Bode diagram of the PWM and LC filter transfer function (GPW0 · GLC(f))
and the open loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEIII(f)) are drawn.
19/36
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