L5986 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L5986' PDF : 39 Pages View PDF
L5986 - L5986A
Application information
minimize the dc error on regulated output voltage; finally to place other poles far away the
zero dB frequency.
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a
frequency higher than the desired bandwidth (that is: 2π∗ESR∗COUT<1/BW), the type III
compensation network is needed. Multi Layer Ceramic capacitors (MLCC) have very low
ESR (<1 mΩ), with very high frequency zero, so type III network is adopted to compensate
the loop.
In Figure 9 the type III compensation network is shown. This network introduces two zeros
(fZ1, fZ2) and three poles (fP0, fP1, fP2). They expression are:
Equation 16
fZ1
=
-----------------------1-------------------------,
2π ⋅ C3 ⋅ (R1 + R3)
fZ2
=
--------------1---------------
2π ⋅ R4 ⋅ C4
Equation 17
fP0 = 0,
fP1
=
--------------1--------------- ,
2π ⋅ R3 ⋅ C3
fP2
=
---------------------1----------------------
2
π
⋅
R4
⋅
-C-----4----⋅---C-----5--
C4 + C5
Figure 9. Type III compensation network
In Figure 10 the Bode diagram of the PWM and LC filter transfer function (GPW0 · GLC(f))
and the open loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEIII(f)) are drawn.
19/39
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