L5988D
Application information
6.4.1
The PWM modulator gain is a function of the switching frequency:
Equation 23
GPW0fSW = GPW0400 kHz f--S----W--4----0-k--0-H-----z---- = 9 f--S----W---4---0-k--0-H-----z----
The transfer function on the LC filter is given by:
Equation 24
where:
GLCs = -1----+------2-----------------1------Q--s--+----------2-------f-----L---------C-----------f-s+---z------E------S-2-----------R-----------s------f----L------C--------2-
Equation 25
fLC
=
-----------------------------------1------------------------------------
2 L COUT 1 + -R-E---O-S---U-R---T-
fzESR = 2------------E----S-----R1---------C----O----U----T-
Equation 26
Q = -----R----O----U--L--T--+-----CL-----O---C-U----TO----U---R-T---O----U--R--T---O----U-E---T--S--+--R---E----S-----R-----,
ROUT = V--I--O-O---U-U--T-T--
Two different kinds of networks can compensate the loop depending on the output capacitor.
Type II network is used to compensate the loop with high ESR output capacitors, type III
with low ESR output capacitors (MLCC). In the two following paragraph the guidelines to
select the Type II and Type III compensation network are illustrated.
Type III compensation network
The methodology to stabilize the loop consists of placing two zeros to compensate the effect
of the LC double pole, so increasing phase margin; then to place one pole in the origin to
minimize the dc error on regulated output voltage; finally to place other poles far away the
zero dB frequency.
In Figure 13 the type III compensation network is shown. This network introduces two zeros
(fZ1, fZ2) and three poles (fP0, fP1, fP2). They expression are:
Equation 27
fZ1 = 2------------C-----7------1---R-----8----+-----R----7----
fZ2 = 2------------R--1---5-------C----5-
Equation 28
fP0 = 0
fP1 = 2------------R--1---7-------C----7-
fP2 = 2------------R-----5----1----C-C-------5--5------+--------C--C--------6--6--
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