L5991 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L5991' PDF : 23 Pages View PDF
Figure 30. Disable (Latched).
DISABLE
SIGNAL
DIS
C
14
+
-
2.5V
D
DISABLE
Q
R
UVLO
D97IN502
connecting DC-LIM to VREF (half duty cycle op-
tion), Dx will be set approximately at:
Dx
≅
2
⋅
RT
RT +
260
(11)
Figure 31. Half duty cycle option.
td
V15=GND
V5=V13=GND
L5991 - L5991A
and the output switching frequency will be halved
with respect to the oscillator one because an in-
ternal T flip-flop (see block diagram) is activated.
Fig. 31 shows the operation.
The half duty cycle option speeds up the dis-
charge of the timing capacitor CT (in order to get
duty cycles as close to 50% as possible) so the
oscillator frequency - with the same timing compo-
nents will be slightly higher.
Pin 16. S-BY (Standby Function). The resistor RB,
along with RA, sets the operating frequency of the
oscillator in normal operation (fosc). In fact, as long
as the STANDBY signal is high, the pin is inter-
nally connected to the reference voltage VREF by
a N-channel FET (see fig. 32), so the timing ca-
pacitor CT is charged through RA and RB. When
the STANDBY signal goes low the N-channel FET
is turned off and the pin becomes floating. RB is
V2
DX =
tc
tc + td
tc
td
V15=VREF
V5=V13=GND
tc
V10
D97IN498
V2
DX =
tc
2 ·tc + td
V10
Figure 32. Standby function internal schematic and operation.
5
FB
-
+
2.5
COMP
6
ISEN
13
+
2R
-
R
R
DRIVER
OUT
10V
+
STANDBY
-
2.5/4
LEVEL SHIFT
STANDBY BLOCK
STANDBY
4
VREF
HIGH
ST-BY
16
LOW
RB
RA
2
RCT
CT
VT1
VT2
2.5V
4V
D97IN752B
VCOMP
13/23
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