L6228Q View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L6228Q' PDF : 32 Pages View PDF
Circuit description
L6228Q
Figure 21. Overcurrent protection simplified schematic
POWER SENSE
1 cell
OUT1A VSA OUT2A
HIGH SIDE DMOSs OF
THE BRIDGE A
μC or LOGIC
VDD
REN. EN
CEN.
I1A I2A
TO GATE
LOGIC
POWER DMOS
n cells
+
OCD
COMPARATOR
I1A / n
INTERNAL
OPEN-DRAIN
RDS(ON)
40Ω TYP.
(I1A+I2A) / n
IREF
OVER TEMPERATURE
POWER DMOS
n cells
I2A / n
POWER SENSE
1 cell
OCD
COMPARATOR
FROM THE
BRIDGE B
D01IN1337
Figure 22 shows the overcurrent detection operation. The disable time tDISABLE before
recovering normal operation can be easily programmed by means of the accurate
thresholds of the logic inputs. It is affected both by CEN and REN values and its magnitude is
reported in Figure 23. The delay time tDELAY before turning off the bridge when an
overcurrent has been detected depends only by CEN value. Its magnitude is reported in
Figure 24.
CEN is also used to provide immunity to pin EN against fast transient noises. Therefore the
value of CEN should be chosen as big as possible according to the maximum tolerable delay
time and the REN value should be chosen according to the desired disable time.
The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended
values for REN and CEN are respectively 100 kΩ and 5.6 nF that allow 200 μs disable time to
be obtained.
20/32
Doc ID 14321 Rev 5
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