L6238 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L6238' PDF : 35 Pages View PDF
1.2 Input Default States
Figure 2: Input Structures
Figure 3: Input Logic
L6238
FUNCTION
PORT DIS
STROBE
PORT CLK
R/W
DATA I/O
EXT/I NT
FREF ENABLE
LIN
OUTPUT ENABLE
RUN/BRAKE
SEQ INCR
SYS CLOCK
EXT INDEX
PLL FREF
CONFIGU RATION
PULL-UP
PULL-DOWN
PULL-UP
PULL-UP
PULL-UP
PULL-DOWN
PULL-DOWN
PULL-DOWN
PULL-DOWN
PULL-UP
PULL-DOWN
PULL-UP
PULL-UP
PULL-UP
Figure 2 depicts the two possible input structures
for the logic inputs. If a particular pin is not used
in an application, it may either be connected to
ground or VLOGIC as required, or simply left un-
connected. If no connection is made, the pin is
either pulled high or low by internal constant cur-
rent generators as shown
A listing of the logic inputs is shown with the cor-
responding default state.
1.3 Naming Convention
In order to differentiate between the various types
of control and status signals, the following naming
convention is used.
BOLD CAPITALS - Device pins.
Italics - Serial port control and status signals.
Three input signals form a special case. Referring
to figure 3, the RUN/BRAKE input pin and the
Run/Brake control signal form a logical AND func-
tion, while OUTPUT ENABLE and Output Enable
form an OR function. The outputs signal names,
in Bold Lower case labeled Run/Brake and Out-
put Enable will be used when referring to these
signals. Although not shown, SEQUENCE IN-
CREMENT and Sequence Increment also form
an OR function, with the resultant output signal
called Sequence Increment.
1.4 Modes of Operation
There are 5 basic modes of operation.
1) Tristate
When Output Enable is low, the output power
drivers are tristated.
2) Start-Up
With Output Enable high, bringing Run/Brake
from a low to a high will energize the motor and
the system will be driven by the Fully-Integrated
StartUp Algorithm. A user-defined Start-Up Algo-
rithm, under control of a MicroProcessor, can be
achieved via a serial port and/or external control
pins.
3) Run
Identified by the Lock signal, Run mode is
achieved when the motor speed (controlled by the
Internal PLL) reaches the nominal speed within a
predefined phase error.
4) Park
When Run/Brake is brought low, energy to park
the heads may be derived from the rectified Bemf.
The energy recovery time is a function of the
Brake Delay Time Constant. In this state, the qui-
escent current of the device is minimized (sleep
mode).
5) Brake
After the Energy Recovery Time-Out, the device
is in Brake, with all lower Drivers in full conduc-
tion.
During a power down, the Park Mode is triggered,
followed by a Dynamic Brake.
There are two mutually exclusive conditions
which may be present during the Tristate Mode
(wake up):
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