L6260 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L6260' PDF : 30 Pages View PDF
L6260
System Control Reg B (Reg 4)
Reg: 4
Name: System Control Register B
Type: Write only
BIT
LABEL
0 FLLGAIN BIT 0
1 FLLGAIN BIT 1
2 FLLGAIN BIT 2
3 EXT_INT
4 CLK_PRESCALE
5 SYNHALL
6 SFETGAIN
7 SLEW BIT 0
8 SLEW BIT 1
9 SLEW BIT 2
10 SLEW BIT 3
11 MASK_PHASE
DESCRIPTION
Frequency Locked Loop (FLL) gain control. A gain factor of 1 to 8
can be programmed, This register value varies the FLL gain by
changing the Integrator Current. Bit 0 is the LSB.
External or internal spindle loop feedback. This bit is programmed
to 0 for BEMF feedback, 1 for external feedback. External
feedback is connected via the DTEST pin, which is configured as
an input in this mode.
This selects a one bit pre-scaler for the internal clock, minimizing
the effect of differing fequencies on the FLL and logic counters.
Set to 1for 4-6MHz system clock, Set to 0 for 8-12MHz system
clock
This selects the signal at the SYNTH_HALL pin.
When set to 0, Synth Hall pin will produce a once per BEMF
crossing signal (from BEMF comparitor). Setting the bit to 1,
Synth Hall pin will give a once per electrical cycle signal (from zero
crossing detector).
Selects the gain of the sense FET circuit of the spindle driver.
0 = Spindle is high transconductance loop gain, 1 = low gain
Slew rate control Bit 0 ( LSB)
Slew rate control Bit 1
Slew rate control Bit 2 (MSB)
Setting this bit to 1 selects an internal 250K slew rate resistor.
Setting it to 0 allows slew rate control by an external resistor.
Selects between 7.5° and 15° mask time (0=15°, 1=7.5°)
@POR
0
0
0
0
0
0
0
0
0
0
0
Figure 2: The following diagram explains bits 5 ”SYNTH HALL” and the effect it has on the pin named
SYNTH_HALL
MOTOR PHASES
Below are the three possible waveforms
available from the SYNTH-HALL pin.
The desired waveform is selected via
”Synth Hall” bits in the System Control
Register B.
Once per ”BEMF Crossing”
(Once per zero cross)
Once per ”electrical cycle”
12/30
D94IN091
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