Pin connection
2
Pin connection
Figure 2. Pins connection (top view)
LIN 1
SD 2
HIN 3
VCC 4
DT 5
OPOUT 6
GND 7
14 BOOT
13 HVG
12 OUT
11 NC
10 LVG
9 OP-
8 OP+
L6392
Table 2. Pin description
Pin N# Pin name
Type
Function
1
LIN
2
SD (1)
3
HIN
4
VCC
5
DT
6
OPOUT
7
GND
8
OP+
9
OP-
10
LVG (1)
11
NC
12
OUT
13
HVG (1)
14
BOOT
I
Low side driver logic input (active low)
I
Shut down logic input (active low)
I
High side driver logic input (active high)
P
Lower section supply voltage
I
Dead time setting
O
Opamp output
P
Ground
I
Opamp non inverting input
I
Opamp inverting input
O
Low side driver output
Not connected
P
High side (floating) common voltage
O
High side driver output
P
Bootstrapped supply voltage
1. The circuit provides less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This allows
to omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low; the gate driver assures low impedance also in SD condition.
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Doc ID 14494 Rev 5