L6460 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L6460' PDF : 139 Pages View PDF
Electrical specifications
L6460
Table 5. Electrical characteristics (continued)
Parameter
Description
Test condition
Min Typ Max Unit
ADChannelX[4:0]
IAD
A/D path absorbed current
=10001 and
-1
bit EnDacScale=0
1
µA
tDELAY
Delay from serial write to pin
low
CLOAD =50 pF(45)
500 ns
SPI interface (40)
VIH
VIL
VHYS
VOH
VOL
tSCLK
tSCLK_rise
tSCLK_fall
tSCLK_high
tSCLK_low
tnSS_setup
tnSS_hold
tnSS_min
tMOSI_setup
tMOSI_hold
tMISO_rise
tMISO_fall
tMISO_valid
tMISO_disable
CLOAD
High level input voltage
Low level input voltage
Input voltage hysteresis
High level output voltage
Low level output voltage
SCLK period
SCLK rise time
SCLK fall time
SCLK high time
SCLK low time
nSS setup time
nSS hold time
nSS high minimum time
MOSI setup time
MOSI hold time
MISO rise time
MISO fall time
MISO valid from clock low
MISO disable time
MOSI maximum load
(46)
(46)
(46)
IOUT = -10mA,(47)
IOUT = 10mA,(47)
CLOAD=50pF(48)
CLOAD=50pF (48)
1.6
V
0.8
V
0.15 0.22
V
2.75
V
0.4
V
62.5
ns
2
ns
2
ns
20
ns
20
ns
10
ns
10
ns
30
ns
10
ns
10
ns
9
ns
9
ns
0
15
ns
0
15
ns
200 pF
1. This value is useful to define the voltage rating for external capacitor to be connected from VSupply to VSupplyInt.
2. This typical value is only intended to give an estimation of the current consumption when L6460 is configured in simple
regulators mode (see following Chapter 8.6.4) at the end of the start up sequence and with no load on regulators. This
typical value allows a raw choose of the external resistor but the definitive choose must be done according to the
recommendations on Chapter 4.1).
3. Measured between 10% and 90% of output voltage transition.
4. Measured from a fault detection to 50% of output voltage transition.
5. Current is defined to be positive when flowing into the pin.
6. Load regulation is calculated at a fixed junction temperature using short load pulses covering all the load current range. This
is to avoid change on output voltage due to heating effect.
7. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VLINmain_FB).
8. Default state.
9. The regulated voltage can be calculated using the formula: VSWmain_OUT = VFBREF *(Ra+Rb)/Rb.
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Doc ID 17713 Rev 1
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