L6460 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L6460' PDF : 139 Pages View PDF
General purpose PWM
19 General purpose PWM
L6460
L6460 includes three general purpose PWM generators that can be redirected on GPIO
pins (see Chapter 22). Two of these generators (Aux_PWM_1 and Aux_PWM_2) work with
a fixed period FOSC/512 and have a programmable duty cycle; the other one (GP_PWM)
has a programmable base time clock and a programmable time for both high and low levels.
19.1
General purpose PWM generators 1 and 2 (AuxPwm1 and
AuxPwm2)
The Duty cycle of these PWM generators can be changed by writing the AuxPwmXCtrl bits
(where X can be 1 or 2) in the AuxPwm1Ctrl and AuxPwm2Ctrl registers. Their positive duty
cycle will change according to the equation:
PWM_X_DUTY = AuxPwmXCtrl[9:0]/512
According to this equation a programmed “0” value will cause a 0% duty cycle (output
always at logic level 0).
19.2
Programmable PWM generator (GpPwm)
GpPWM has a programmable base clock that can be changed by programming the
GpPwmBase[6:0] bits in the GpPwmBase register. The clock will change according to the
equation:
PWM_BASE_PERIOD = (GpPwmBase[6:0] + 1) × Tosc
The high and low level duration (expressed in base clock periods), can be programmed
writing the GpPwmHigh[7:0] and GpPwmLow[7:0] bits in the GpPwmCtrl register so they will
change according to following equations:
High_level_Time = GpPwmHigh[7:0] × PWM_BASE_PERIOD
Low_level_Time = GpPwmLow[7:0] × PWM_BASE_PERIOD
The resulting period of the PWM will be:
Period = (GpPwmHigh[7:0] + GpPwmLow[7:0]) + PWM_BASE_PERIOD
and the positive duty cycle will result:
DutyCycle
=
--------------------------H----i-g----h---_---l--e---v---e---l--_---T----i-m-----e---------------------------
High_level_Time + Low_level_Time
=
-G-----p---P-----w----m------H----Gi--g---p-h---P[---7-w--:--0-m---]--H-+----i-G-g---h-p---[-P-7---w-:--0--m--]---L----o----w-----[--7----:-0----]
A programmed value of 0 in GpPwmHigh[7:0] and GpPwmLow[7:0] bits will force the PWM
generator output to be always at logic level “0”.
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Doc ID 17713 Rev 1
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