L6566A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L6566A' PDF : 52 Pages View PDF
Application information
L6566A
Figure 20. Operation after latched disable activation: timing diagram
DIS
(pin 8)
4.5V
Vcc
(pin 5)
VccON
VccON -0.5
VccOFF
HV generator is turned on
Vccrestart
GD
(pin 4)
Restart is quicker
t
Disable latch is reset here
t
HV generator turn-on is disabled here
Vcc_PFC
t
(pin 6)
Vin
Input source is removed here
t
VHVstart
AC_OK
t
(pin 16)
Vth
t
5.10
Soft-start and delayed latched shutdown upon overcurrent
At device startup, a capacitor (Css) connected between the SS pin (14) and ground is
charged by an internal current generator, ISS1, from zero up to about 2 V where it is
clamped. During this ramp, the overcurrent setpoint progressively rises from zero to the
value imposed by the voltage on the VFF pin 15, (see Section 5.6); MOSFET conduction
time increases gradually, therefore controlling the startup inrush current. The time needed
for the overcurrent setpoint to reach its steady-state value, referred to as soft-start time, is
approximately:
Equation 9
TSS
=
Css
ISS1
Vcsx
(VVFF
)
=
Css
ISS1
⎜⎜⎝⎛1
−
VVFF
3
⎟⎟⎠⎞
During the ramp (i.e. until VSS = 2 V) all the functions that monitor the voltage on the COMP
pin are disabled.
The soft-start pin is also invoked whenever the control voltage (COMP) saturates high,
which reveals an open-loop condition for the feedback system. This condition very often
occurs at startup, but may be also caused by either a control loop failure or a converter
overload/short-circuit. A control loop failure results in an output overvoltage that is handled
by the OVP function of the L6566A (see Section 5.11). In the case of QR operation, a short-
circuit causes the converter to run at a very low frequency, then with very low power
capability. This causes the self-supply system that powers the device to switch off, so that
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Doc ID 13794 Rev 4
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