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L6566BH View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
L6566BH
ST-Microelectronics
STMicroelectronics ST-Microelectronics
'L6566BH' PDF : 51 Pages View PDF
Application information
L6566BH
Cycle-by-cycle current limitation is realized with a second comparator (OCP comparator)
that senses the voltage across the current sense resistor Rs as well and compares this
voltage to a reference value VCSX. Its output is OR-ed with that of the PWM comparator (see
the circuit schematic in Figure 17). In this way, if the programming signal delivered by the
feedforward block and sent to the PWM comparator exceeds VCSX, it is the OCP comparator
to reset first the PWM latch instead of the PWM comparator. The value of Vcsx, thereby,
determines the overcurrent setpoint along with the sense resistor Rs.
The power that QR flyback converters with a fixed overcurrent setpoint (like fixed-frequency
systems) are able to deliver changes considerably with the input voltage. With wide-range
mains, at maximum line it can be more than twice the value at minimum line, as shown by
the upper curve in the diagram of Figure 16. The device has the line feedforward function
available to solve this issue.
It acts on the overcurrent setpoint VCSX, so that it is a function of the converter’s input voltage
Vin sensed through a dedicated pin (15, VFF): the higher the input voltage, the lower the
setpoint. This is illustrated in the diagram on the left-hand side of Figure 17: it shows the
relationship between the voltage on the pin VFF and VCSX (with the error amplifier saturated
high in the attempt to obtain output voltage regulation):
Equation 5
Vcsx
= 1VVFF
3
= 1k Vin
3
Figure 16. Typical power capability change vs. input voltage in QR flyback
converters
2.5
k=0
2
system not
compensated
k
1.5
Note:
1
system optimally
compensated
k = kopt
0.5
1
1.5
2
2.5
3
3.5
4
AM11492v1
If the voltage on the pin exceeds 3 V, switching ceases but the soft-start capacitor is not
discharged. The schematic in Figure 17 shows also how the function is included in the
control loop.
With a proper selection of the external divider R1-R2, i.e. of the ratio k = R2 / (R1+R2), it is
possible to achieve the optimum compensation described by the lower curve in the diagram
of Figure 16.
The optimum value of k, kopt, which minimizes the power capability variation over the input
voltage range, is the one that provides equal power capability at the extremes of the range.
The exact calculation is complex, and non-idealities shift the real-world optimum value from
26/51
Doc ID 16610 Rev 2
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