System control loop compensation
21 System control loop compensation
L6713A
The control loop is composed by the current sharing control loop (See Figure 9) and the
average current mode control loop. Each loop gives, with a proper gain, the correction to the
PWM in order to minimize the error in its regulation: the current sharing control loop
equalize the currents in the inductors while the average current mode control loop fixes the
output voltage equal to the reference programmed by VID. Figure 25 shows the block
diagram of the system control loop.
The system control loop is reported in Figure 26. The current information IDROOP sourced by
the DROOP pin flows into RFB implementing the dependence of the output voltage from the
read current.
Figure 25. Main control loop
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L3
PWM3
L2
PWM2
L1
PWM1
ERROR AMPLIFIER
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CURRENT SHARING
DUTY CYCLE
CORRECTION
IINFO1
IINFO2
IINFO3
COMP
(PHASE2 Only applies when using 3-PHASE Operation)
ZF(s)
COUT
ROUT
VREF
IDROOP
FB
DROOP
ZFB(s)
The system can be modeled with an equivalent single phase converter which only difference
is the equivalent inductor L/N (where each phase has an L inductor). The control loop gain
results (obtained opening the loop after the COMP pin):
GLOOP(s)
=
–--------------P----W------M-------⋅---Z----F---(--s----)---⋅---(---R----D----R----O----O----P----+-----Z----P----(--s---)---)--------------
[ZP(s) + ZL(s)] ⋅ Z--A--F--(--(-s-s--)-)- + ⎝⎛1 + A-----(1--s----)⎠⎞ ⋅ RFB
Where:
● DCR is the Inductor parasitic resistance;
●
RDROOP
function;
=
D-----C-----R---
Rg
⋅
RF
B
is
the
equivalent
output resistance
determined
by
the
droop
● ZP(s) is the impedance resulting by the parallel of the output capacitor (and its ESR)
and the applied load RO;
● ZF(s) is the compensation network impedance;
● ZL(s) is the parallel of the N inductor impedance;
● A(s) is the error amplifier gain;
●
PWM
=
4--
5
⋅
-----V-----I-N-------
ΔVOSC
is the PWM transfer function where ΔVOSC is the oscillator ramp
amplitude and has a typical value of 3 V.
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