Detailed description
5.3
Slope compensation
L6928
In current mode architecture, when the duty cycle of the application is higher than
approximately 50%, a pulse-by-pulse instability (so-called subharmonic oscillation) can
occur. In these conditions, to allow loop stability, a slope compensation is present by
reducing the current flowing through the inductor to trigger the COMP comparator (with a
fixed value for the COMP pin voltage). With a given duty cycle higher than 50%, the
stability problem is particularly present with a higher input voltage (due to the increased
current ripple across the inductor), so the slope compensation effect increases as the input
voltage increases. From an application point of view, the final effect is that the peak current
limit depends both on the duty cycle (if higher than approximately 40%) and on the input
voltage.
5.4
Loop stability
Since the device is developped by a current mode architecture, the loop stability is usually
not an issue. For most of applications, a 220 pF connected between the COMP pin and
ground can guarantee the stability. Very low ESR capacitors are used for the output filter,
such as multilayer ceramic capacitors, the zero introduced by the capacitor itself can shift
to very high frequency and the transient loop response could be affected. A series resistor
added to the 220 pF capacitor can solve this problem. The right value for the resistor (in the
range of 50 k) can be given by checking the load transient response of the device.
Basically, the output voltage has to be checked at the scope after the load steps required
by the application. In case of stability problems, the output voltage could oscillate before
than the regulated value is reached after a load step.
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