LF3320 View Datasheet(PDF) - LOGIC Devices
Part Name
Description
MFG CO.
'LF3320' PDF : 24 Pages View PDF
DEVICES INCORPORATED
LF3320
Horizontal Digital Image Filter
TABLE 4. CONFIGURATION REGISTER 2 – ADDRESS 202H
BITS FUNCTION
DESCRIPTION
0
ALU Mode Filter B
0: A + B
1: B – A
1
Pass A Filter B
0 : ALU Input A = 0
1 : ALU Input A = Forward Register Path
2
Pass B Filter B
0 : ALU Input B = 0
1 : ALU Input B = Reverse Register Path
11-3 Reserved
Must be set to “0”
TABLE 5. CONFIGURATION REGISTER 3 – ADDRESS 203H
BITS FUNCTION
DESCRIPTION
0
Filter B Odd-Tap
Interleave Mode
0 : Odd-Tap Interleave Mode Disabled
1 : Odd-Tap Interleave Mode Enabled
4-1
Filter B I/D Register Length 0000 :
0001 :
0010 :
0011 :
0100 :
0101 :
0110 :
0111 :
1000 :
1001 :
1010 :
1011 :
1100 :
1101 :
1110 :
1111 :
1 Register
2 Registers
3 Registers
4 Registers
5 Registers
6 Registers
7 Registers
8 Registers
9 Registers
1 0 Registers
1 1 Registers
1 2 Registers
1 3 Registers
1 4 Registers
1 5 Registers
1 6 Registers
5
Filter B Tap Number
0 : Even Number of Taps
1 : Odd Number of Taps
6
Filter B Data Reversal
0 : Data Reversal Enabled
1 : Data Reversal Disabled
11-7 Reserved
Must be set to “0”
Output Limiting
An output limiting function is provided for
the overall filter, Filter A, and Filter B
outputs. The Filter A limiting circuitry is
used to limit the overall filter output (Single
Filter Mode) and the Filter A output (Dual
Filter Mode). The Filter B limiting circuitry
is used to limit the Filter B output (Dual
Filter Mode). The Filter A and B limit
registers determine the valid range of
output values for the Filter A and B
limiting circuitry respectively. There are
sixteen 32-bit user-programmable limit
registers for both Filters A and B. The Filter
A limit registers are used for the overall
filter (Single Filter Mode) or Filter A (Dual
Filter Mode). The Filter B limit registers are
used for Filter B (Dual Filter Mode).
RSLA3-0 determines which of the sixteen
Filter A limit registers are used in the Filter
A limit circuitry. RSLB3-0 determines
which of the sixteen Filter B limit
registers are used in the Filter B limit
circuitry. A value of 0 on
RSLA/RSLB3-0 selects Filter A/B limit
register 0. A value of 1 selects Filter A/B
limit register 1 and so on. Each limit
register contains an upper and lower
limit value. If the value fed to the
limiting circuitry is less than the lower
limit, the lower limit value is passed as
the filter output. If the value fed to the
limiting circuitry is greater than the
upper limit, the upper limit value is
passed as the filter output. Bit 1 and 0
in Configuration Register 4 enable and
disable Filter A and B limiting respec-
tively. RSLA/RSLB3-0 may be changed
every clock cycle if desired. This allows
the limit range to be changed every clock
cycle. This is useful when filtering
interleaved data. When loading limit
values into the device, the upper limit
must be greater than the lower limit.
Limit register loading is discussed in the
LF InterfaceTM section.
Coefficient Banks
The coefficient banks store the coeffi-
cients which feed into the multipliers
in Filters A and B. There is a separate
bank for each multiplier. Each bank
can hold 256 12-bit coefficients. The
banks are loaded using an LF
InterfaceTM. There is a separate LF
InterfaceTM for the Filter A and B
banks. Coefficient bank loading is
discussed in the LF InterfaceTM
section.
Configuration and Control Registers
The configuration registers determine
how the LF3320 operates. Tables 2
through 7 show the formats of the six
configuration registers. There are three
types of control registers: round, select,
and limit. There are sixteen round
registers for Filter A and sixteen for
Filter B. Each register is 32 bits wide.
RSLA3-0 and RSLB3-0 determine which
Filter A and B round registers respec-
tively are used for rounding.
There are sixteen select registers for
Filter A and sixteen for Filter B. Each
register is 5 bits wide. RSLA3-0 and
RSLB3-0 determine which Filter A and B
select registers respectively are used in
the select circuitry.
Video Imaging Products
2-14
08/16/2000–LDS.3320-N
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