LF43168JC15 View Datasheet(PDF) - LOGIC Devices

Part Name

Description

MFG CO.

LF43168JC15

Dual 8-Tap FIR Filter

LOGIC Devices 

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DEVICES INCORPORATED

LF43168

Dual 8-Tap FIR Filter

SIGNAL DEFINITIONS

Power

VCC and GND

+5 V power supply. All pins must be

connected.

Clock

CLK — Master Clock

The rising edge of CLK strobes all

enabled registers.

Inputs

INA9-0 — Data Input (FIR Filter A)

INA9-0 is the 10-bit registered data

input port for FIR Filter A. INA9-0

can also be used to send data to FIR

Filter B. Data is latched on the

rising edge of CLK.

FIGURE 2A. INPUT FORMATS

Data

Coefficient

Fractional Unsigned

987

20 2–1 2–2

210

2–7 2–8 2–9

987

20 2–1 2–2

210

2–7 2–8 2–9

987

–20 2–1 2–2

(Sign)

Fractional Two's Complement

210

2–7 2–8 2–9

987

–20 2–1 2–2

(Sign)

210

2–7 2–8 2–9

FIGURE 2B. OUTPUT FORMATS

Fractional Unsigned

27 26 25

29 28 27

210

2–16 2–17 2–18

Fractional Two's Complement

27 26 25

–29 28 27

(Sign)

210

2–16 2–17 2–18

INB9-0 — Data Input (FIR Filter B)

INB9-0 is the 10-bit registered data

input port for FIR Filter B. Data is

latched on the rising edge of CLK.

INB9-1 is also used as OUT8-0, the nine

least significant bits of the data output

port (see OUT27-0 section).

CIN9-0 — Coefficient/Control Data Input

CIN9-0 is the data input port for the

coefficient and control registers. Data

is latched on the rising edge of WR.

A8-0 — Coefficient/Control Address

Outputs

OUT27-0 — Data Output

OUT27-0 is the 28-bit registered data

output port. OUT8-0 is also used as

INB9-1, the nine most significant bits

of the FIR Filter B data input port (see

INB9-0 section). If both filters are

configured for even-symmetric

coefficients, and both input and

coefficient data is unsigned, the filter

output data will be unsigned. Other-

wise, the output data will be in two’s

complement format.

A8-0 provides the write address for data Controls

on CIN9-0. Data is latched on the

falling edge of WR.

SHFTEN — Shift Enable

WR — Coefficient/Control Write

The rising edge of WR latches data on

CIN9-0 into the coefficient/control

register addressed by A8-0.

CSEL4-0 — Coefficient Select

CSEL4-0 determines which set of

coefficients is sent to the multipliers in

both FIR filters. Data is latched on the

rising edge of CLK.

When SHFTEN is LOW, data on

INA9-0 and INB9-0 can be latched into

the device and data can be shifted

through the decimation registers.

When SHFTEN is HIGH, data on

INA9-0 and INB9-0 can not be latched

into the device and data in the input

and decimation registers is held. This

signal is latched on the rising edge

of CLK.

3

FWRD — Forward ALU Input

When FWRD is LOW, data from the

forward decimation path is sent to the

“A” inputs on the ALUs. When

FWRD is HIGH, “0” is sent to the “A”

inputs on the ALUs. This signal is

latched on the rising edge of CLK.

RVRS — Reverse ALU Input

When RVRS is LOW, data from the

reverse decimation path is sent to the

“B” inputs on the ALUs. When RVRS

is HIGH, “0” is sent to the “B” inputs

on the ALUs. This signal is latched on

the rising edge of CLK.

TXFR — LIFO Transfer Control

When TXFR goes LOW, the LIFO

sending data to the reverse decimation

path becomes the LIFO receiving data

from the forward decimation path,

and the LIFO receiving data from the

forward decimation path becomes the

LIFO sending data to the reverse

decimation path. The device must see

a HIGH to LOW transition of TXFR in

order to switch LIFOs. This signal is

latched on the rising edge of CLK.

Video Imaging Products

03/28/2000–LDS.43168-H

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