LH28F008SCB-L12 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F008SCB-L12' PDF : 55 Pages View PDF
sharp
LHF08CH1
21
Start
Write 60H,
Block/Device Address
Write 01H/F1H,
Block/Device Address
Read
Status Register
0
SR.7=
1
Full Status
Check if Desired
Set Lock-Bit
Complete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
1
SR.3=
0
VPP Range Error
1
SR.1=
Device Protect Error
0
1
SR.4,5=
0
Command Sequence
Error
1
SR.4=
0
Set Lock-Bit Successful
Set Lock-Bit Error
Bus
Operation
Write
Write
Command
Comments
Set
Block/Master
Lock-Bit Setup
Set
Block or Master
Lock-Bit Confirm
Data=60H
Addr=Block Address(Block),
Device Address(Master)
Data=01H(Block),
F1H(Master)
Addr=Block Address(Block),
Device Address(Master)
Read
Status Register Data
Standby
Check SR.7
1=WSM Ready
0=WSM Busy
Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-bit set operation
or after a sequence of lock-bit set operations.
Write FFH after the last lock-bit set operation to place device in
read array mode.
Bus
Operation
Command
Comments
Standby
Standby
Check SR.3
1=VPP Error Detect
Check SR.1
1=Device Protect Detect
RP#=VIH
(Set Master Lock-BIt Operation)
RP#=VIH, Master Lock-Bit is Set
(Set Block Lock-BIt Operation)
Standby
Check SR.4,5
Both 1=Command
Sequence Error
Standby
Check SR.4
1=Set Lock-Bit Error
SR.5,SR.4,SR.3 and SR.1 are only cleared by the Clear Status
Register command in cases where multiple lock-bits are set before
full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
Figure 9. Set Block and Master Lock-Bit Flowchart
Rev. 1.3
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