LH28F008SCB-V90 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F008SCB-V90' PDF : 40 Pages View PDF
LH28F008SC-V/SCH-V
6.2.7 RESET OPERATIONS
VOH
RY/BY# (R)
VOL
VIH
RP# (P)
VIL
VOH
RY/BY# (R)
VOL
VIH
RP# (P)
VIL
tPLPH
(A) Reset During Read Array Mode
tPLRH
tPLPH
(B) Reset During Block Erase, Byte Write, or Lock-Bit Configuration
VCC
5V
VIL
VIH
RP# (P)
VIL
t5VPH
(C) RP# Rising Timing
Fig. 15 AC Waveform for Reset Operation
Reset AC Specifications (NOTE 1)
SYMBOL
PARAMETER
tPLPH
RP# Pulse Low Time (If RP# is tied to VCC,
this specification is not applicable)
NOTE
VCC = 5.0±0.5 V
MIN.
MAX.
100
UNIT
ns
tPLRH
t5VPH
RP# Low to Reset during Block Erase,
Byte Write or Lock-Bit Configuration
VCC 4.5 V to RP# High
2, 3
4
100
12
µs
ns
NOTES :
1. These specifications are valid for all product versions
(packages and speeds).
2. If RP# is asserted while a block erase, byte write, or
lock-bit configuration operation is not executing, the reset
will complete within 100 ns.
3. A reset time, tPHQV, is required from the latter of RY/BY#
or RP# going high until outputs are valid.
4. When the device power-up, holding RP#-low minimum
100 ns is required after VCC has been in predefined
range and also has been in stable there.
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