LH28F320S5B-L100 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F320S5B-L100' PDF : 61 Pages View PDF
sharp
LHF32K10
42
6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES(1)
Versions(5)
VCC=5V±0.5V, 5V±0.25V, TA=0°C to +70°C
VCC=5V±0.25V LH28F320S5-L90(6)
VCC=5V±0.5V
LH28F320S5-
L100(7)
Sym.
Parameter
Notes Min.
Max.
Min.
Max.
Unit
tAVAV Write Cycle Time
90
100
ns
tPHEL RP# High Recovery to CE# Going Low 2
1
1
µs
tWLEL WE# Setup to CE# Going Low
0
0
ns
tELEH CE# Pulse Width
50
50
ns
tSHEH WP# VIH Setup to CE# Going High
2
100
100
ns
tVPEH VPP Setup to CE# Going High
2
100
100
ns
tAVEH Address Setup to CE# Going High
3
40
40
ns
tDVEH Data Setup to CE# Going High
3
40
40
ns
tEHDX Data Hold from CE# High
5
5
ns
tEHAX Address Hold from CE# High
5
5
ns
tEHWH WE# Hold from CE# High
0
0
ns
tEHEL CE# Pulse Width High
25
25
ns
tEHRL CE# High to STS Going Low
90
90
ns
tEHGL Write Recovery before Read
0
0
ns
tQVVL VPP Hold from Valid SRD, STS High Z 2,4
0
0
ns
tQVSL WP# VIH Hold from Valid SRD, STS
High Z
2,4
0
0
ns
NOTES:
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold and
inactive WE# times should be measured relative to the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid AIN and DIN for block erase, full chip erase, (multi) word/byte write or block lock-bit
configuration.
4. VPP should be held at VPPH1 until determination of block erase, full chip erase, (multi) word/byte write or block
lock-bit configuration success (SR.1/3/4/5=0).
5. See Ordering Information for device speeds (valid operational combinations).
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed
Configuration) for testing characteristics.
7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard
Configuration) for testing characteristics.
Rev. 1.55
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