LH28F320S5B-L90 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F320S5B-L90' PDF : 61 Pages View PDF
sharp
LHF32K10
21
Table 14. Status Register Definition
WSMS
BESS
ECBLBS WSBLBS
VPPS
WSS
DPS
R
7
6
5
4
3
2
1
0
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
SR.6 = BLOCK ERASE SUSPEND STATUS
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS
STATUS
1 = Error in Erase or Clear Blocl Lock-Bits
0 = Successful Erase or Clear Block Lock-Bits
SR.4 = WRITE AND SET BLOCK LOCK-BIT STATUS
1 = Error in Write or Set Block Lock-Bit
0 = Successful Write or Set Block Lock-Bit
SR.3 = VPP STATUS
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.2 = WRITE SUSPEND STATUS
1 = Write Suspended
0 = Write in Progress/Completed
SR.1 = DEVICE PROTECT STATUS
1 = Block Lock-Bit and/or WP# Lock Detected,
Operation Abort
0 = Unlock
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
NOTES:
Check STS or SR.7 to determine block erase, full chip
erase, (multi) word/byte write or block lock-bit
configuration completion.
SR.6-0 are invalid while SR.7="0".
If both SR.5 and SR.4 are "1"s after a block erase, full
chip erase, (multi) word/byte write, block lock-bit
configuration or STS configuration attempt, an improper
command sequence was entered.
SR.3 does not provide a continuous indication of VPP
level. The WSM interrogates and indicates the VPP level
only after block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration command
sequences. SR.3 is not guaranteed to reports accurate
feedback only when VPP≠VPPH1.
SR.1 does not provide a continuous indication of block
lock-bit values. The WSM interrogates block lock-bit,
and WP# only after block erase, full chip erase, (multi)
word/byte write or block lock-bit configuration command
sequences. It informs the system, depending on the
attempted operation, if the block lock-bit is set and/or
WP# is not VIH. Reading the block lock configuration
codes after writing the Read Identifier Codes command
indicates block lock-bit status.
SR.0 is reserved for future use and should be masked
out when polling the status register.
Table 14.1. Extended Status Register Definition
SMS
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
NOTES:
XSR.7 = STATE MACHINE STATUS
1 = Multi Word/Byte Write available
After issue a Multi Word/Byte Write command: XSR.7
0 = Multi Word/Byte Write not available
indicates that a next Multi Word/Byte Write command is
available.
XSR.6-0=RESERVED FOR FUTURE ENHANCEMENTS
XSR.6-0 is reserved for future use and should be
masked out when polling the extended status register.
Rev. 1.55
Share Link: 
