LH28F800SGHB-L70 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F800SGHB-L70' PDF : 45 Pages View PDF
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
6.2.3 DC CHARACTERISTICS (contd.)
SYMBOL
PARAMETER
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
Output High Voltage
VOH1
(TTL)
Output High Voltage
VOH2
(CMOS)
VPP Lockout Voltage during
VPPLK
Normal Operations
VPP Voltage during
VPPH1 Word Write, Block Erase
or Lock-Bit Operations
VPP Voltage during
VPPH2 Word Write, Block Erase
or Lock-Bit Operations
VPP Voltage during
VPPH3 Word Write, Block Erase
or Lock-Bit Operations
VLKO VCC Lockout Voltage
VHH RP# Unlock Voltage
NOTE VCC = 2.7 to 3.6 V VCC = 5.0±0.5 V UNIT
MIN. MAX. MIN. MAX.
TEST
CONDITIONS
7 –0.5 0.8 –0.5 0.8 V
VCC
VCC
7
2.0
2.0
V
+0.5
+0.5
VCC = VCC Min.
3, 7
0.4
0.45 V IOL = 5.8 mA (VCC = 5 V),
IOL = 2.0 mA (VCC = 3.3 V, 2.7 V)
VCC = VCC Min.
3, 7 2.4
2.4
V IOH = –2.5 mA (VCC = 5 V),
IOH = –2.0 mA (VCC = 3.3 V, 2.7 V)
0.85
VCC
3, 7
VCC
– 0.4
0.85
VCC
VCC
– 0.4
V VCC = VCC Min.
IOH = –2.5 µA
V VCC = VCC Min.
IOH = –100 µA
4, 7
1.5
1.5 V
2.7
3.6
—
—V
4.5
5.5
4.5
5.5 V
11.4 12.6 11.4 12.6 V
2.0
2.0
V
Set permanent lock-bit
8 11.4 12.6 11.4 12.6 V
Override block lock-bit
NOTES :
1. All currents are in RMS unless otherwise noted. Typical
values at nominal VCC voltage and TA = +25°C. These
currents are valid for all product versions (packages and
speeds).
2. ICCWS and ICCES are specified with the device de-
selected. If reading or word writing in erase suspend
mode, the device’s current draw is the sum of ICCWS or
ICCES and ICCR or ICCW, respectively.
3. Includes RY/BY#.
4. Block erases, word writes, and lock-bit configurations are
inhibited when VPP ≤ VPPLK, and not guaranteed in the
range between VPPLK (max.) and VPPH1 (min.), between
VPPH1 (max.) and VPPH2 (min.), between VPPH2 (max.)
and VPPH3 (min.), and above VPPH3 (max.).
5. Automatic Power Saving (APS) reduces typical ICCR to
1 mA at 5 V VCC and 3 mA at 2.7 to 3.6 V VCC in static
operation.
6. CMOS inputs are either VCC±0.2 V or GND±0.2 V. TTL
inputs are either VIL or VIH.
7. Sampled, not 100% tested.
8. Permanent lock-bit set operations are inhibited when
RP# = VIH. Block lock-bit configuration operations are
inhibited when the permanent lock-bit is set or RP# =
VIH and WP# = VIL. Block erases and word writes are
inhibited when the corresponding block lock-bit is set
and RP# = VIH and WP# = VIL or the permanent lock-bit
is set. Block erase, word write, and lock-bit configuration
operations are not guaranteed with VIH < RP# < VHH
and should not be attempted.
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