LH28F800SGHB-L70 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F800SGHB-L70' PDF : 45 Pages View PDF
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
6.2.6 AC CHARACTERISTICS FOR CE#-CONTROLLED WRITE OPERATIONS (NOTE 1)
• VCC = 2.7 to 3.0 V, TA = 0 to +70˚C or –40 to +85˚C
VERSIONS
SYMBOL
PARAMETER
tAVAV Write Cycle Time
tPHEL RP# High Recovery to CE# Going Low
tWLEL WE# Setup to CE# Going Low
tELEH CE# Pulse Width
tPHHEH RP# VHH Setup to CE# Going High
tVPEH VPP Setup to CE# Going High
tAVEH Address Setup to CE# Going High
tDVEH Data Setup to CE# Going High
tEHDX Data Hold from CE# High
tEHAX Address Hold from CE# High
tEHWH WE# Hold from CE# High
tEHEL CE# Pulse Width High
tEHRL CE# High to RY/BY# Going Low
tEHGL Write Recovery before Read
tQVVL VPP Hold from Valid SRD, RY/BY# High
tQVPH RP# VHH Hold from Valid SRD, RY/BY# High
NOTE
2
2
2
3
3
2, 4
2, 4
LH28F800SG-L70
LH28F800SGH-L70
MIN.
MAX.
100
1
0
70
100
100
50
50
5
5
0
25
100
0
0
0
LH28F800SG-L10
LH28F800SGH-L10
MIN.
MAX.
120
1
0
70
100
100
50
50
5
5
0
25
100
0
0
0
UNIT
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
• VCC = 3.3±0.3 V, TA = 0 to +70˚C or –40 to +85˚C
VERSIONS
SYMBOL
PARAMETER
tAVAV Write Cycle Time
tPHEL RP# High Recovery to CE# Going Low
tWLEL WE# Setup to CE# Going Low
tELEH CE# Pulse Width
tPHHEH RP# VHH Setup to CE# Going High
tVPEH VPP Setup to CE# Going High
tAVEH Address Setup to CE# Going High
tDVEH Data Setup to CE# Going High
tEHDX Data Hold from CE# High
tEHAX Address Hold from CE# High
tEHWH WE# Hold from CE# High
tEHEL CE# Pulse Width High
tEHRL CE# High to RY/BY# Going Low
tEHGL Write Recovery before Read
tQVVL VPP Hold from Valid SRD, RY/BY# High
NOTE
2
2
2
3
3
2, 4
LH28F800SG-L70
LH28F800SGH-L70
MIN.
MAX.
85
1
0
70
100
100
50
50
5
5
0
25
100
0
0
LH28F800SG-L10
LH28F800SGH-L10
MIN.
MAX.
100
1
0
70
100
100
50
50
5
5
0
25
100
0
0
UNIT
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tQVPH RP# VHH Hold from Valid SRD, RY/BY# High 2, 4
0
0
ns
NOTES :
1. In systems where CE# defines the write pulse width
3. Refer to Table 3 for valid AIN and DIN for block erase,
(within a longer WE# timing waveform), all setup, hold,
word write, or lock-bit configuration.
and inactive WE# times should be measured relative to
the CE# waveform.
2. Sampled, not 100% tested.
4. VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block erase,
word write, or lock-bit configuration success (SR.1/3/4/5 = 0).
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