LH540205D-25 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH540205D-25' PDF : 17 Pages View PDF
CMOS 8192 × 9 Asynchronous FIFO
TIMING DIAGRAMS (cont’d)
LH540205
D0 - D8
VALID DATA IN
W
tRPE
R
EF
t WEF
t WLZ
tREF
tA
Q0 - Q8
VALID DATA OUT
NOTES:
1. tRPE = tRPW
2. tRPE: Effective Read Pulse Width after Empty Flag HIGH.
3. The Data Out pins (D0 - D8) are forced into a
high-impedance state whenever EF = LOW.
Figure 13. Read Data Flow-Through
540205-8
R
tWPF
W
t RFF
FF
t WFF
D0 - D8
tA
Q0 - Q8
VALID DATA OUT
NOTES:
1. tWPF = tWPW.
2. tWPF: Effective Write Pulse Width after Full Flag HIGH.
Figure 14. Write Data Flow-Through
t DS
t DH
VALID DATA IN
540205-9
13
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