LH543611M-15 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH543611M-15' PDF : 57 Pages View PDF
LH543611/21
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
OPERATIONAL DESCRIPTION (cont’d)
which otherwise would be permissible for that speed
grade of LH543611/21.
When a FIFO full condition is reached, write operations
are locked out. Following the first read operation from a
full FIFO, another memory location is freed up, and the
corresponding Full Flag is deasserted (FF = HIGH). The
first write operation should begin no earlier than a First
Write Latency (tFWL) after the first read operation from a
full FIFO, to ensure that correct read data are retrieved.
(See Figures 33 and 34.)
FIFO Read
Port A reads from FIFO #2, and Port B reads from FIFO
#1. A read operation is initiated on the rising edge of a
clock (CKA or CKB) whenever: the appropriate enable
(ENA or ENB) is held HIGH; the appropriate request
(REQA or R EQB) is held HIGH; the appropri ate
Read/Write control (R/WA or R/WB) is held HIGH;
the FIFO address is selected for the address inputs
(A2A – A0A or A0B); and the prescribed setup times and
hold times are observed for all of these signals. Read data
becomes valid on the data-bus pins (D0A – D35A or
D0B – D35B) by a time tA after the rising clock (CKA or
CKB) edge, provided that the data outputs are enabled.
OEA and OEB are assertive-LOW, asynchronous, Out-
put Enable control input signals. Their effect is only to
enable or disable the output drivers of the respective port.
Disabling the outputs does not disable a read operation;
data transmitted to the corresponding output register will
remain available later, when the outputs again are en-
abled, unless it subsequently is overwritten.
When an empty condition is reached, read operations
are locked out until a valid write operation(s) has loaded
additional data into the FIFO. Following the first write to
an empty FIFO, the corresponding empty flag (EF) will be
deasserted (HIGH). The first read operation should begin
no earlier than a First Read Latency (tFRL) after the first
write to an empty FIFO, to ensure that correct read data
words are retrieved. (See Figures 31 and 32.)
Dedicated FIFO Status Flags
Six dedicated FIFO status flags are included for Full
(FF1 and FF2), Half-Full (HF1 and HF2), and Empty (EF1
and EF2). FF1, HF1, and EF1 indicate the status of FIFO
#1; and FF2, HF2, and EF2 indicate the status of FIFO #2.
A Full Flag is asserted following the first subsequent
rising clock edge for a write operation which fills the FIFO.
A Full Flag is deasserted following the first subsequent
falling clock edge for a read operation to a full FIFO. A
Half-Full Flag is updated following the first subsequent
rising clock edge of a read or write operation to a FIFO
which changes its ‘half-full’ status. An Empty Flag is
asserted following the first subsequent rising clock edge
for a read operation which empties the FIFO. An Empty
Flag is deasserted following the falling clock edge for a
write operation to an empty FIFO.
Programmable Status Flags
Four programmable FIFO status flags are provided,
two for Almost-Full (AF1 and AF2), and two for Almost-
Empty (AE1 and AE2). Thus, each port has two program-
mable flags to monitor the status of the two internal FIFO
buffer memories. The offset values for these flags are
initialized to eight locations from the respective FIFO
boundaries during reset, but can be reprogrammed over
the entire FIFO depth.
An Almost-Full Flag is asserted following the first sub-
sequent rising clock edge after a write operation which
has partially filled the FIFO up to the ‘almost-full’ offset
point. An Almost-Full Flag is deasserted following the first
subsequent falling clock edge after a read operation
which has partially emptied the FIFO down past the
‘almost-full’ offset point. An Almost-Empty Flag is
asserted following the first subsequent rising clock edge
after a read operation which has partially emptied
the FIFO down to the ‘almost-empty’ offset point. An
Almost-Empty Flag is deasserted following the first sub-
sequent falling clock edge after a write operation which
has partially filled the FIFO up past the ‘almost-empty’
offset point.
Flag offsets may be written or read through the Port A
data bus. All four programmable FIFO status flag offsets
can be set simultaneously through a single 36-bit status
word; or, each programmable flag offset can be set indi-
vidually, through one of four nine-bit (LH543611) or ten-bit
(LH543621) status words. Tables 3a and 3b illustrate the
data format for flag-programming words. Note that when
all four offsets are set simultaneously in an LH543621,
the settings are limited to magnitudes expressible in nine
bits; for larger offset values, the individual setting option
must be used. (See Figure 3b.)
Also, Tables 4a and 4b define the meaning of each of
the five flags, both the dedicated flags and the program-
mable flags, for the LH543611 and LH543621 respec-
tively.
NOTE: Control inputs which may affect the computation
of flag values at a port generally should not change while
the clock for that port is HIGH, since some updating of
flag values takes place on the falling edge of the clock.
Mailbox Operation
Two mailbox registers are provided for passing system
hardware or software control/status words between ports.
Each port can read its own mailbox and write to the other
port’s mailbox. Mailbox access is performed on the rising
edge of the controlling FIFO’s clock, with the mailbox
address selected and the enable (ENA or ENB) HIGH.
That is, writing to Mailbox Register #1, or reading from
Mailbox Register #2, is synchronized to CKA; and writing
to MailboxRegister #2, or reading from Mailbox Register
#1, is synchronized to CKB.
The R/WA/B and OEA/B pins control the direction and
availability of mailbox-register accesses. Each mailbox
register has its own New-Mail-Alert Flag (MBF1 and
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