LH543611M-15 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH543611M-15' PDF : 57 Pages View PDF
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS (cont’d)
LH543611/21
CKA (CKB)
tRWS tRWH
R/WA (R/WB)
ENA (ENB)
tES
tEH
tRQS tRQH
REQA (REQB)
tFF
tSKEW1 (4)
tFF
FF1 (FF2)
CKB (CKA)
tRWS tRWH
R/WB (R/WA)
tES
tEH
ENB (ENA)
tRQS tRQH
REQB (REQA)
NOTES:
1. A2A, A1A, and A0A all are held HIGH for FIFO access at Port A.
A0B is held HIGH for FIFO access at Port B.
2. Parameters without parentheses apply to FIFO #1 operation.
Parameters with parentheses apply to FIFO #2 operation.
3. Assertion of the Full Flags is controlled by rising clock edges;
whereas, internal deassertion of the Full Flags is controlled by
falling clock edges, and their external deassertion is controlled
by rising clock edges.
4. tSKEW1 is the minimum time between a falling CKB (CKA) edge
and a rising CKA (CKB) edge for FF to change predictably during
the current clock cycle. If the time between the falling edge of
CKB (CKA) and the rising edge of CKA (CKB) is less than tSKEW1,
then it is not guaranteed that FF will change state until the next
following CKA (CKB) edge.
Figure 23. Full Flag Timing, When Synchronous
543611-46
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