LH543621 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH543621' PDF : 57 Pages View PDF
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
TIMING DIAGRAMS
t RS
RS, FR1, FR2
t RSS
t RSH
t RSS
CKA
ENA
t ES
t EH
tRQS
tRQH
t ES
t EH
tRQS
tRQH
REQA
CKB
t RSS
t ES
t EH
t RSH
t RSS
t ES
t EH
ENB
REQB
tRQS
tRQH
t RF
tRQS
tRQH
EF, AE
t RF
HF, AF, FF, MBF
NOTES:
1. RS overrides all other input signals, except for R/WA, ENA, and REQA. It operates
asynchronously. RS, FR1, and FR2 operates whether or not ENA and/or ENB are asserted.
At least one rising edge and one falling edge of both CKA and CKB must occur while
RS is being asserted (is LOW), with timing as defined by tRSS and tRSH.
2. Otherwise, tRSS, tRSH need not be met unless the rising edge of CKA and/or CKB
occurs while that clock is enabled.
3. The parity-check even/odd selection (Control Register bit 00) is initialized to odd byte
parity at reset (HIGH). All other Control Register bits are initialized LOW. FR1 and FR2
do not alter the configuration, flags reflect the absence of data.
4. The AE and AF flag offsets are initialized to eight locations from the boundary at reset
controlled by RS.
Figure 11. Reset Timing
LH543611/21
543611-19
23
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