LH543621P-30 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH543621P-30' PDF : 57 Pages View PDF
512 x 36 x 2/1024 x 36 x 2 BiFIFOs
LH543611/21
TIMING DIAGRAMS (cont’d)
CKA (CKB)
tRWS
Outside the 'almost-full' region,
acknowledge is continuous
for a continuous request.
***
Starting at the third cycle after entering the
'almost-full' region, acknowledge
occurs on every third cycle to prevent overrun
of the full condition.
*
*
R/WA (R/WB)
tRQS
REQ A (REQB)
t ACK
t ACK
t ACK
t ACK
ACK A (ACKB)1
t AF
2
AF1 (AF2)
NOTES:
1. For a FIFO access to occur, REQ and EN must be held HIGH for the required setup and hold times.
2. ACK can be tied directly to EN to directly gate FIFO accesses.
* Indicates where a write would take place, if ACK were tied to EN.
3. REQ must be maintained HIGH with R/W stable throughout entire clock cycle for ACK to be generated.
4. When the REQ/ACK handshake is not used, ACK can be ignored,
and REQ may be tied HIGH or used as a second enable.
5. Parameters without parentheses apply to Port A. Parameters with parentheses apply to Port B.
Figure 39. Write Request/Acknowledge Handshake
543611-41
51
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