LH5PV16256 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH5PV16256' PDF : 14 Pages View PDF
CMOS 4M (256 × 16) Pseudo-Static RAM
LH5PV16256
TRUTH TABLE
CE CS RFSH OE
L
H
H
L
L
H
H
X
H
X
L
X
L
L
H
X
H
X
H
X
NOTES:
H = High
L = Low
X = Don’t care
UWE
H
H
L
L
H
X
X
X
LWE
H
L
H
L
H
X
X
X
MODE
Word Read
Lower byte write
Write
Upper byte write
Word write
Invalid
Auto refresh
CS standby
Standby
I/O0 - 7
Output data
Input data
Don’t care
Input data
High-Z
High-Z
High-Z
High-Z
I/O8 - 15
Output data
Don’t care
Input data
Input data
High-Z
High-Z
High-Z
High-Z
REQUIREMENTS
2WE control
Please do not separate the UWE and LWE operation timing intentionally in the same write cycles. Each of the
UWE/LWE should satisfy the timing specifications individually.
Refresh after self-refresh or data retention mode
• If address refresh is used during normal read/write cycles, the first address refresh must be executed within
15 µs after self-refresh or data retention mode ends and the address refresh must be executed continuously for
2,048 refresh cycles.
• If distributed auto-refresh is used during normal read/write cycles, the first auto-refresh must be executed within
15 µs after self-refresh or data retention mode ends.
• If burst auto-refresh is used during normal read/write cycles, the first auto-refresh must be executed within
15 µs after self-refresh or data retention mode ends, and the auto-refresh must be executed continuously for
2,048 refresh cycles.
Bypass capacitor for power supply noise reduction
Because a PSRAM operates dynamically like a DRAM, it is recommended to put bypass capacitors between VCC
and GND to absorb power supply noise due to the peak current.
3
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