SHARI=
.. ;
RESET OPERATIONS
LHFlGKA7
STS(R)
High Z
VOL
VIH
RP#(P)
VIL
High Z
STS( R)
VOL
VIH
RP#(P)
4
ML
tpLPH
(A)Reset During Read Array Mode
(B)Reset During Block Erase, Full Chip Erase, (Multi) Word/Byte Write
or Block Lock-Bit Configuretion
2.7f3.3V
vcc
WL
VIH
RP#( P)
VIL
I
I-
(C)Vcc Power Up Timing
Figure 21. AC Waveform for Reset Operation
Reset AC Specifications
V,.,=2.7V
vr.c=3.3v
Symbol
Parameter
Notes Min.
Max.
Min.
Max. Unit
tPLPH
RP#/ Pulse Low Time
(If RP# is tied to Vcc, this specification is
100
100
ns
not applicable)
tPLRH
RP# Low to Reset during Block Erase,
Full Chip Erase, (Multi) Word/Byte Write
1,2
21.5
21.1
IJS
or Block Lock-Bit Configuration
t23VPH Vcc at 2.7V to RP# High
Vcn at 3.OV to RP# High
3 - 100
100
ns
MOTES:
1. If RP# is asserted while a block erase, full chip erase, (multi) word/byte write or block lock-bit configuration
operation is not executing, the reset will complete within 1OOns.
3. A reset time, tpHov, is required from the latter of STS going High Z or RP# going high until outputs are valid.
3. When the device power-up, holding RP# low minimum 1OOns is required after Vcc has been in predefined range
and also has been in stable there.
L
Rev. 1.9