sharp
LHF32KZ5
36
6.2.2 AC INPUT/OUTPUT TEST CONDITIONS
2.7
INPUT
1.35
TEST POINTS
1.35 OUTPUT
0.0
AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 14. Transient Input/Output Reference Waveform for VCC=2.7V-3.6V
3.0
INPUT
1.5
TEST POINTS
1.5
OUTPUT
0.0
AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 15. Transient Input/Output Reference Waveform for VCC=3.3V±0.3V and VCC=5V±0.25V
(High Speed Testing Configuration)
3.0
INPUT
1.5
TEST POINTS
1.5
OUTPUT
0.0
AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 16. Transient Input/Output Reference Waveform for VCC=5V±0.5V
(Standard Testing Configuration)
1.3V
1N914
DEVICE
UNDER
TEST
CL Includes Jig
Capacitance
RL=3.3kΩ
OUT
CL
Test Configuration Capacitance Loading Value
Test Configuration
VCC=3.3V±0.3V, 2.7V-3.6V
VCC=5V±0.25V
VCC=5V±0.5V
CL(pF)
50
30
50
Figure 17. Transient Equivalent Testing
Load Circuit