SHARP
SPEC No.
LC99404
MODEL
No.
Livl7MS623
PAGE
15
Because of the characteristics of the CMOS driver LSI, the power consumption of the display module goes up
as the operating frequency CP2. Thanks to the 4 lines of shift registers to reduce the data transfer speed CP2
Thanks to the LSI, the power consumption of the display module will be minimized.
In this circuit configuration, 4-bit display data shalI be therefore input to data input pins of DO -3.
Furthermore, the display module has bus line system for data input to minimize the power consumption with
data input termin& of each driver LSI being activated only when relevant data input is fed.
Data input for column electrodes and chip select of driver LSI are made as follows:
The driver LSI at the left end of the display face is first selected, and the adjacent driver LSI of the right
next side is selected when data of 160 dot (4OCP2) is fed. This process is sequentially continued until data is
fed to the driver LSI at the right end of the display face.
Thus data input will be made through 4-bit bus line sequentially from the left end of the display face.
Since this display module contains no refresh RAM, it requires the above data and timing pulse inputs even for
static display.
The timing chart of input signals are shown in fig. 3 and Table 7.