NXP Semiconductors
LPC1102/1104
32-bit ARM Cortex-M0 microcontroller
6
IDD
(mA)
4
2
002aaf982
48 MHz(2)
36 MHz(2)
24 MHz(2)
12 MHz(1)
0
−40
−15
10
35
60
85
temperature (°C)
Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the
SYSAHBCLKCTRL register (SYSAHBCLKCTRL= 0x1F); all peripheral clocks disabled; internal
pull-up resistors disabled; BOD disabled; low-current mode.
(1) System PLL disabled; IRC enabled.
(2) System PLL enabled; IRC disabled.
Fig 8. Sleep mode: Typical supply current IDD versus temperature for different system
clock frequencies
5.5
IDD
(μA)
4.5
002aaf977
3.5
VDD = 3.3 V, 3.6 V
2.5
1.8 V
1.5
−40
−15
10
35
60
85
temperature (°C)
Fig 9.
Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register
(PDSLEEPCFG = 0x0000 18FF).
Remark: Before entering deep-sleep mode, you must write a 0 to bit 4 and bit 5 of the GPIO0DATA
register at location 0x5000 3FFC and a 1 to bit 4 and bit 5 of the GPIO0DIR register at location
0x5000 8000.
Deep-sleep mode: Typical supply current IDD versus temperature for different
supply voltages VDD
LPC1102_1104
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 26 September 2013
© NXP B.V. 2013. All rights reserved.
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